1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip, and more particularly, to IC design migration.
2. Background Art
Technology remapping requires scaling of IC layouts. Typically, the scaling of an IC design is not uniform for all ground rules. To solve this issue, conventional approaches use an optimizer to scale all components of an IC layout and then use another optimizer to fix up potential ground-rule errors. Constraints may be applied to perform the scaling in a non-uniform fashion.
An IC layout with macros built from a common cell library presents a special difficulty because the macros are customized and the base cells are standardized. Here, a macro is made up of circuit rows, each circuit row including library cells abutting one another. One conventional approach to the macro migration issue puts all macros to be migrated in a single super-cell to process. Under this approach, all sub-cells are migrated simultaneously with the respective top-level cell, and all top-level cells are migrated simultaneously and in relation to one another. Here, a sub-cell and a top-level cell are defined with respect to the hierarchical structure of an IC design. Such an approach would be expensive from the perspective of time and data volume. In addition, it might not be known which top-level cells need to be migrated ahead of time, which makes this approach difficult unsuitable.
Another approach to the macro migration issue migrates top-level cells and sub-cells separately. Top-level cells are re-assembled using the migrated versions of the data in the macros and the migrated versions of the sub-cells. One drawback of this approach is the fact that the environments of the top level cells are not known when the sub-cells are migrated, and vice versa. A further drawback is that electrical shorts or opens can result between shape in a sub-cell and shapes in a macro. In this case, a large amount of manual fix-up may be required to rebuild the top-level cell.